The present invention relates to semiconductor fabrication and in particular to self-aligned silicide technology.
Silicide technology is improving the performance characteristics of semiconductor devices, and is becoming an essential component of semiconductor device fabrication. As gate electrode lengths are scaled down, the source/drain junctions and polycrystalline line width must also be scaled down. However, scaling down the source/drain junctions and polycrystalline line width increases parasitic, sheet, and contact resistance in the source/drain diffusion layers and gate electrode diffusion layer. Silicidizing active regions of substrates reduces parasitic, sheet, and contact resistance in the source/drain diffusion layers and gate electrode diffusion layer. Silicide technology comprises forming silicide layers on the source/drain regions and/or on the gate electrode in a self-aligned manner.
Silicides are typically formed by reacting a metal with crystallized silicon (Si) within a specified temperature range for a specific period of time. Silicide layers may be self-aligned by different techniques. For example, selectively depositing the metal on the top of the gate electrode and on the source/drain regions of a semiconductor device prior to an annealing process causes only the Si of the source/drain regions and the top of the gate electrode to form silicide upon annealing. Alternatively, sidewall spacers on the sides of the gate electrode comprising of a material that does not react with the metal layer allow a blanket layer of metal to be deposited over a semiconductor device while restricting silicide formation to a portion of the exposed source/drain regions during an annealing process. During the annealing process, the semiconductor device is heated to a reaction temperature, and held at the reaction temperature for a period of time, causing the metal layer to react with the crystallized Si that the metal contacts, thus forming a silicide layer interfacing with the remaining crystallized Si substrate of the source/drain regions and/or the gate electrode. Multiple annealing steps may be employed. Various metals react with Si to form a silicide including but not limited to Co, Ni, Pt, Ti, W, etc.
The thickness of the silicide layer is an important parameter because a thin silicide layer is more resistive than a thicker silicide layer of the same material; thus a thicker silicide layer increases semiconductor device speed. Conventional silicide technology for reducing parasitic series resistance has proven problematic, particularly as design rules plunge into the deep-submicron range. For example, the formation of a thick suicide layer may cause a high junction leakage current and low reliability, particularly when forming ultra-shallow junctions. The formation of a thick silicide layer consumes silicon from the underlying semiconductor substrate such that the thick silicide layer approaches and even shorts the ultra-shallow junction, thereby generating a high junction leakage current.
Recently, attention has turned towards using nickel to form NiSi utilizing silicide technology. Using NiSi is advantageous over using TiSi2 and CoSi2 because many limitations associated with TiSi2 and CoSi2 are avoided. When forming NiSi, a low resistivity phase is the first phase to form, and does so at a relatively low temperature. Additionally, nickel (Ni), like Co, diffuses through the film into Si, unlike Ti where the Si diffuses into the metal layer. Diffusion of Ni, and Co, through the film into Si prevents bridging between the silicide layer on the gate electrode and the silicide layer over the source/drain regions. The reaction that forms NiSi requires less Si than when TiSi2 and CoSi2 are formed. Nickel silicide exhibits almost no line-width dependence of sheet resistance. Nickel silicide also exhibits low film stress, i.e., causes less wafer distortion.
In addition to the formation of silicide on the active regions, silicide is also normally formed on the polysilicon gate electrode""s upper surface. It is desirable to lower the resistance of the gate electrode to increase the speed of the device. The greater the amount of silicon converted into silicide in the gate electrode, the lower the resistance will be in the gate electrode. However, formation of silicide on the gate electrode simultaneously with the source/drain regions leads to the risk of spiking in the source/drain regions, if the complete silicidation of the gate electrode is attempted. This is due to the strong likelihood that exposure of the metal and silicon to rapid thermal annealing conditions sufficient to completely silicidize a gate electrode will also cause the silicide to spike and reach the bottom of a junction, undesirably causing current leakage. There is a need for a method of forming a substantially fully silicidized gate electrode while avoiding the spiking of a source/drain region in a semiconductor device.
These and other needs are met by embodiments of the present invention of forming a fully silicidized gate on a substrate having active regions, the method comprising the steps of forming silicide on the active regions of the substrate; and fully silicidizing the gate..
Another aspect of the present invention is a method of forming a fully silicidized gate on a substrate having active regions, the method comprising the steps of: forming silicide on the active regions; providing a shielding layer over the substrate leaving the gate exposed; depositing a metal on the gate; and annealing to cause the metal to react with the gate thereby substantially fully silicidizing the gate.
An advantage of the present invention is a semiconductor device having active regions and, more particularly, a gate region comprising low resistivity contacts and exhibiting reduced parasitic series resistance, especially in the gate region, and exhibiting reduced leakage current.
Additional advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein embodiments of the present invention are described simply by way of illustrating the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.